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107 lines
2.9 KiB
107 lines
2.9 KiB
2 months ago
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/** @defgroup flash_file FLASH peripheral API
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*
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* @ingroup peripheral_apis
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai @m@matthewlai.ca>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/flash.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Issue Pipeline Stall
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Issue a pipeline stall to make sure all write operations completed.
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RM0385: After performing a data write operation and before polling the BSY bit
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to be cleared, the software can issue a DSB instruction to guarantee the
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completion of a previous data write operation.
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*/
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static inline void flash_pipeline_stall(void)
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{
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__asm__ volatile("dsb":::"memory");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Wait until Last Operation has Ended
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This loops indefinitely until an operation (write or erase) has completed by
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testing the busy flag.
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*/
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void flash_wait_for_last_operation(void)
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{
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flash_pipeline_stall();
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the Erase Sequence Error Flag
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This flag is set when an erase operation is performed with control register has
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not been correctly set.
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*/
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void flash_clear_erserr_flag(void)
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{
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FLASH_SR |= FLASH_SR_ERSERR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear All Status Flags
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Program error, end of operation, write protect error.
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*/
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void flash_clear_status_flags(void)
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{
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flash_clear_erserr_flag();
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flash_clear_pgaerr_flag();
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flash_clear_wrperr_flag();
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flash_clear_pgperr_flag();
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flash_clear_eop_flag();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the ART Cache
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*/
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void flash_art_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_ARTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Reset the ART Cache
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The ART cache must be disabled for this to have effect.
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*/
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void flash_art_reset(void)
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{
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FLASH_ACR |= FLASH_ACR_ARTRST;
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}
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/**@}*/
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