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79 lines
2.7 KiB
79 lines
2.7 KiB
3 months ago
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/**
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* @brief <b>PAC55xxxx Memory Controller Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date April 1, 2020
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*
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* This library supports the Memory Controller in the PAC55xx SoC from Qorvo.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/pac55xx/memctl.h>
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void memctl_flash_set_wstate(uint32_t wstate) {
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MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_WSTATE(MEMCTL_MEMCTLR_WSTATE_MASK)) | MEMCTL_MEMCTLR_WSTATE(wstate);
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}
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void memctl_flash_set_mclkdiv(uint32_t div) {
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MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_MCLKDIV(16)) | MEMCTL_MEMCTLR_MCLKDIV(div);
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}
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void memctl_flash_reset_write_buffer(void) {
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MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_WRITEWORDCNT(MEMCTL_MEMCTLR_WRITEWORDCNT_MASK));
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}
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void memctl_flash_standby_mode_enable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_STBY;
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}
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void memctl_flash_standby_mode_disable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_STBY;
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}
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void memctl_flash_cache_enable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_CACHEDIS;
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}
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void memctl_flash_cache_disable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_CACHEDIS;
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}
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void memctl_flash_select_roscclk(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_MCLKSEL;
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}
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void memctl_flash_select_mclk(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_MCLKSEL;
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}
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void memctl_sram_ecc_enable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_ECCDIS;
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}
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void memctl_sram_ecc_disable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_ECCDIS;
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}
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void memctl_sram_ecc_single_bit_interrupt_enable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_SEIE;
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}
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void memctl_sram_ecc_single_bit_interrupt_disable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_SEIE;
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}
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void memctl_sram_ecc_dual_bit_interrupt_enable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_DEIE;
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}
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void memctl_sram_ecc_dual_bit_interrupt_disable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_DEIE;
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}
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void memctl_invaddr_interrupt_enable(void) {
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MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_INVADDRIE;
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}
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void memctl_invaddr_interrupt_disable(void) {
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MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_INVADDRIE;
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}
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