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608 lines
19 KiB
608 lines
19 KiB
3 months ago
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!!omap
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- ADC0_CR:
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fields: !!omap
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- SEL:
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access: rw
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description: Selects which of the ADCn_[7:0] inputs are to be sampled and
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converted
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lsb: 0
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reset_value: '0'
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width: 8
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- CLKDIV:
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access: rw
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description: The ADC clock is divided by the CLKDIV value plus one to produce
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the clock for the A/D converter
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lsb: 8
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reset_value: '0'
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width: 8
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- BURST:
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access: rw
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description: Controls Burst mode
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lsb: 16
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reset_value: '0'
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width: 1
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- CLKS:
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access: rw
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description: This field selects the number of clocks used for each conversion
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in Burst mode and the number of bits of accuracy of the result in the LS
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bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
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lsb: 17
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reset_value: '0'
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width: 3
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- PDN:
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access: rw
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description: Power mode
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lsb: 21
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reset_value: '0'
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width: 1
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- START:
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access: rw
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description: Controls the start of an A/D conversion when the BURST bit is
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0
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lsb: 24
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reset_value: '0'
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width: 3
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- EDGE:
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access: rw
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description: Controls rising or falling edge on the selected signal for the
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start of a conversion
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lsb: 27
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reset_value: '0'
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width: 1
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- ADC1_CR:
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fields: !!omap
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- SEL:
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access: rw
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description: Selects which of the ADCn_[7:0] inputs are to be sampled and
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converted
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lsb: 0
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reset_value: '0'
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width: 8
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- CLKDIV:
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access: rw
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description: The ADC clock is divided by the CLKDIV value plus one to produce
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the clock for the A/D converter
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lsb: 8
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reset_value: '0'
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width: 8
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- BURST:
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access: rw
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description: Controls Burst mode
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lsb: 16
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reset_value: '0'
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width: 1
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- CLKS:
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access: rw
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description: This field selects the number of clocks used for each conversion
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in Burst mode and the number of bits of accuracy of the result in the LS
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bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
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lsb: 17
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reset_value: '0'
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width: 3
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- PDN:
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access: rw
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description: Power mode
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lsb: 21
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reset_value: '0'
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width: 1
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- START:
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access: rw
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description: Controls the start of an A/D conversion when the BURST bit is
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0
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lsb: 24
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reset_value: '0'
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width: 3
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- EDGE:
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access: rw
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description: Controls rising or falling edge on the selected signal for the
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start of a conversion
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lsb: 27
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reset_value: '0'
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width: 1
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- ADC0_GDR:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADCn pin selected by the SEL field, divided by the reference
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voltage on the VDDA pin
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lsb: 6
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reset_value: '0'
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width: 10
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- CHN:
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access: r
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description: These bits contain the channel from which the LS bits were converted
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lsb: 24
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reset_value: '0'
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width: 3
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an analog-to-digital conversion completes.
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It is cleared when this register is read and when the AD0/1CR register is
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written
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_GDR:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADCn pin selected by the SEL field, divided by the reference
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voltage on the VDDA pin
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lsb: 6
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reset_value: '0'
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width: 10
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- CHN:
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access: r
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description: These bits contain the channel from which the LS bits were converted
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lsb: 24
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reset_value: '0'
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width: 3
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an analog-to-digital conversion completes.
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It is cleared when this register is read and when the AD0/1CR register is
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written
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_INTEN:
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fields: !!omap
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- ADINTEN:
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access: rw
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description: These bits allow control over which A/D channels generate interrupts
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for conversion completion
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lsb: 0
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reset_value: '0'
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width: 8
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- ADGINTEN:
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access: rw
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description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
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When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
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interrupts.
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lsb: 8
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reset_value: '1'
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width: 1
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- ADC1_INTEN:
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fields: !!omap
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- ADINTEN:
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access: rw
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description: These bits allow control over which A/D channels generate interrupts
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for conversion completion
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lsb: 0
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reset_value: '0'
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width: 8
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- ADGINTEN:
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access: rw
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description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
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When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
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interrupts.
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lsb: 8
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reset_value: '1'
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width: 1
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- ADC0_DR0:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC0 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_DR0:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC0 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_DR1:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC1 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_DR1:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC1 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_DR2:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC2 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_DR2:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC2 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC0_DR3:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC3 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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lsb: 30
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reset_value: '0'
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width: 1
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- DONE:
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access: r
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description: This bit is set to 1 when an A/D conversion completes.
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lsb: 31
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reset_value: '0'
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width: 1
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- ADC1_DR3:
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fields: !!omap
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- V_VREF:
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access: r
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description: When DONE is 1, this field contains a binary fraction representing
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the voltage on the ADC3 pin divided by the reference voltage on the VDDA
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pin
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lsb: 6
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reset_value: '0'
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||
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width: 10
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- OVERRUN:
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access: r
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description: This bit is 1 in burst mode if the results of one or more conversions
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was (were) lost and overwritten before the conversion that produced the
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result in the V_VREF bits in this register.
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||
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lsb: 30
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||
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reset_value: '0'
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||
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width: 1
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||
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- DONE:
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access: r
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||
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description: This bit is set to 1 when an A/D conversion completes.
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||
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lsb: 31
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||
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reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC0_DR4:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC1_DR4:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC0_DR5:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC1_DR5:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC0_DR6:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC1_DR6:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC0_DR7:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC1_DR7:
|
||
|
|
fields: !!omap
|
||
|
|
- V_VREF:
|
||
|
|
access: r
|
||
|
|
description: When DONE is 1, this field contains a binary fraction representing
|
||
|
|
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
|
||
|
|
pin
|
||
|
|
lsb: 6
|
||
|
|
reset_value: '0'
|
||
|
|
width: 10
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: This bit is 1 in burst mode if the results of one or more conversions
|
||
|
|
was (were) lost and overwritten before the conversion that produced the
|
||
|
|
result in the V_VREF bits in this register.
|
||
|
|
lsb: 30
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: This bit is set to 1 when an A/D conversion completes.
|
||
|
|
lsb: 31
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|
||
|
|
- ADC0_STAT:
|
||
|
|
fields: !!omap
|
||
|
|
- DONE:
|
||
|
|
access: r
|
||
|
|
description: These bits mirror the DONE status flags that appear in the result
|
||
|
|
register for each A/D channel.
|
||
|
|
lsb: 0
|
||
|
|
reset_value: '0'
|
||
|
|
width: 8
|
||
|
|
- OVERRUN:
|
||
|
|
access: r
|
||
|
|
description: These bits mirror the OVERRRUN status flags that appear in the
|
||
|
|
result register for each A/D channel.
|
||
|
|
lsb: 8
|
||
|
|
reset_value: '0'
|
||
|
|
width: 8
|
||
|
|
- ADINT:
|
||
|
|
access: r
|
||
|
|
description: This bit is the A/D interrupt flag. It is one when any of the
|
||
|
|
individual A/D channel Done flags is asserted and enabled to contribute
|
||
|
|
to the A/D interrupt via the ADINTEN register.
|
||
|
|
lsb: 16
|
||
|
|
reset_value: '0'
|
||
|
|
width: 1
|