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121 lines
3.5 KiB
121 lines
3.5 KiB
/** @defgroup pwr_file PWR peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32G4xx Power Control</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* @author @htmlonly © @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* @date 29 July 2020
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*
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* This library supports the power control system for the
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* STM32G4 series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
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* Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/pwr.h>
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void pwr_set_vos_scale(enum pwr_vos_scale scale)
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{
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uint32_t reg32;
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reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT);
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reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT;
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PWR_CR1 = reg32;
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}
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/** Disable Backup Domain Write Protection
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*
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* This allows backup domain registers to be changed. These registers are write
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* protected after a reset.
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*/
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void pwr_disable_backup_domain_write_protect(void)
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{
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PWR_CR1 |= PWR_CR1_DBP;
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}
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/** Re-enable Backup Domain Write Protection
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*
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* This protects backup domain registers from inadvertent change.
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*/
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void pwr_enable_backup_domain_write_protect(void)
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{
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PWR_CR1 &= ~PWR_CR1_DBP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Select the low power mode used in deep sleep.
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* @param lpms low power mode @ref pwr_cr1_lpms
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*/
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void pwr_set_low_power_mode_selection(uint32_t lpms)
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{
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uint32_t reg32;
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reg32 = PWR_CR1;
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reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT);
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PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable Power Voltage Detector.
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* @param[in] pvd_level Power Voltage Detector Falling Threshold voltage @ref pwr_pls.
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*/
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void pwr_enable_power_voltage_detect(uint32_t pvd_level)
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{
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uint32_t reg32;
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reg32 = PWR_CR2;
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reg32 &= ~(PWR_CR2_PLS_MASK << PWR_CR2_PLS_SHIFT);
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PWR_CR2 = (reg32 | (pvd_level << PWR_CR2_PLS_SHIFT) | PWR_CR2_PVDE);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable Power Voltage Detector.
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*/
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void pwr_disable_power_voltage_detect(void)
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{
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PWR_CR2 &= ~PWR_CR2_PVDE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable Boost Mode.
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*/
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void pwr_enable_boost(void)
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{
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PWR_CR5 &= ~PWR_CR5_R1MODE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable Boost Mode.
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*/
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void pwr_disable_boost(void)
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{
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PWR_CR5 |= PWR_CR5_R1MODE;
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}
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/**@}*/
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